1. Field of the Invention
The present invention generally relates to integrated circuits and, in particular, to systems and methods for facilitating, within an integrated circuit, driver clock-to-output delay testing of pads of the integrated circuit.
2. Description of the Related Art
Heretofore, integrated circuit (IC) devices have been tested and verified using a variety of test methods. For example, IC devices have been tested and verified to be defect-free using functional test vectors, such as those applied to the IC by the use of automated test equipment (ATE), which stimulate and verify the IC device functionality at the pin level of the device. A practical limitation to the utilization of ATE for testing IC""s, however, is that the number of IC pins (or pads) that can be tested by a particular ATE has, heretofore, been limited by the physical configuration of the ATE. For instance, the number of pads of the IC to be tested may exceed the number of test channels provided by an ATE, or the number of pads may exceed the capacity of the ATE support hardware, such as by exceeding the maximum number of probes on a probe card, among others. As utilized herein, the term xe2x80x9cpadxe2x80x9d is used to refer collectively to both a physical site, which serves as an electrical contact for an IC, as well as circuitry associated with the physical site for enabling electrical communication between components of the IC and components external to the IC.
Additionally, performance limitations of a particular ATE may impose certain other testing restrictions. For example, the frequency of IC inputs and outputs may exceed the maximum frequency of the ATE, thereby limiting the test frequency of the IC to be tested to the maximum frequency of the ATE. Although configuring an ATE with additional test channels and/or a higher operating frequency may be accomplished, providing an ATE with an appropriately high pin count and/or an appropriately high operating frequency in order to eliminate the aforementioned deficiencies is, oftentimes, cost prohibitive.
In light of the foregoing and other deficiencies, it is known in the prior art to test IC devices utilizing a variety of xe2x80x9cstop-gapxe2x80x9d testing procedures, including: (1) connecting an ATE to less than all of the pins of an IC device; (2) connecting multiple pins of an IC device to a single ATE test channel; (3) testing the IC device in multiple passes of the ATE, with each pass testing a subset of the pins of the entire IC device; (4) testing the device at less than maximum frequency, and; (5) limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE, among others. As should be readily apparent, many of these xe2x80x9cstop-gapxe2x80x9d testing procedures may result in a loss of test coverage and, thereby, may lead to an increase in numbers of defective IC devices being shipped. Moreover, the practice of limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE is, oftentimes, an unacceptable constraint on IC design.
Referring now to FIG. 1, a representative prior art integrated circuit 100 incorporating built-in self-test circuitry will be described in greater detail. As shown in FIG. 1, integrated circuit 100 includes a core 110 which incorporates logic 112 and digital self-test circuitry 114. Core 110 electrically communicates with pad 116 which is configured to electrically communicate with devices external to the integrated circuit, such as a piece of automated test equipment (ATE) 118, for example. So configured, signals provided from an external device, e.g., ATE 118, may be delivered to the core 110 via a transmission path which includes pad 116.
As is known, digital self-test circuitry 114 is configured to provide functional-based digital testing of logic circuitry contained within core 110. In order to accomplish such testing, digital self-test circuitry 114 typically incorporates a stimulus generator 120 and a response analyzer 122. More specifically, stimulus generator 120 is configured to provide one or more test patterns for testing logic circuitry of the core. The pattern or patterns provided to the logic circuitry are comprised of digital data, i.e., zeros and ones. In response to the various patterns, the logic circuitry under test then provides a response signal or signals to the response analyzer 122 which is able to interpret the response and provide a test result signal, which may be provided externally of the integrated circuit. Thus, the digital self-test circuitry provides for digital, functional testing of the core by applying digital test patterns to the logic circuitry of the core and has, heretofore, substantially removed the need for external test equipment, i.e., ATE 118, to provide stimulus to and check responses from the integrated circuit for facilitating testing of the digital logic circuitry.
Digital self-test circuitry, however, is largely unable to remedy the foregoing and/or other deficiencies. Therefore, there is a need for improved systems and methods which address the aforementioned and/or other shortcomings of the prior art.
Briefly described, the present invention provides driver clock-to-output (henceforth called xe2x80x9cclock-to-qxe2x80x9d) testing functionality within integrated circuits. In this regard, some embodiments of the present invention may be construed as providing integrated circuits (IC""s). In a preferred embodiment, the integrated circuit includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. The first receiver also is configured to provide, to a component internal to the IC, a first receiver digital output signal in response to the first pad input signal. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver clock-to-q time of the first pad.
Some embodiments of the present invention may be construed as providing systems for measuring the driver clock-to-q times of pads of an integrated circuit. In this regard, a preferred system includes an IC and ATE. The ATE is configured to electrically interconnect with the IC and to provide at least one stimulus to the IC. The IC includes a first pad that incorporates a first driver, a first receiver, and a first test circuit. So configured, the first test circuit may electrically communicate with the ATE so that, in response to receiving at least one stimulus from the ATE, the first test circuit provides information corresponding to the driver clock-to-q time of at least one of the pads to the ATE.
Some embodiments of the present invention may be construed as providing methods for testing an IC. In this regard, a preferred method includes the steps of: electrically interconnecting ATE with the IC; providing at least one stimulus such that the IC measures the driver clock-to-q time of the first pad; and receiving information corresponding to the driver clock-to-q time of the first pad.
Other embodiments of the present invention may be construed as providing computer-readable media. In this regard, a preferred computer readable medium, which incorporates a computer program for facilitating measuring of the driver clock-to-q times of pads of an IC includes logic configured to enable ATE to provide at least one stimulus to the IC. Additionally, logic configured to enable the ATE to receive information corresponding to the driver clock-to-q time of at least one of the pads of the IC is provided.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such features and advantages be included herein within the scope of the present invention, as defined in the appended claims.